Digital Electronics and Verilog/VHDL

Unit-1 (12 Lectures, Marks : 15)

Number System and Codes: Decimal, Binary, Hexadecimal and Octal number systems, base conversions,
Binary, octal and hexadecimal arithmetic (addition, subtraction by complement method, multiplication),
representation of signed and unsigned numbers, Binary Coded Decimal code.
Logic Gates and Boolean algebra: Introduction to Boolean Algebra and Boolean operators, Truth Tables of
OR, AND, NOT, Basic postulates and fundamental theorems of Boolean algebra, Truth tables, construction
and symbolic representation of XOR, XNOR, Universal (NOR and NAND) gates.
Digital Logic families: Fan-in, Fan out, Noise Margin, Power Dissipation, Figure of merit, Speed power
product, TTL and CMOS families and their comparison.

Unit-2 (12 Lectures, Marks : 15)

Combinational Logic Analysis and Design: Standard representation of logic functions (SOP and POS),
Karnaugh map minimization, Encoder and Decoder, Multiplexers and Demultiplexers, Implementing logic
functions with multiplexer, binary Adder, binary subtractor, parallel adder/subtractor.

Unit-3 (18 Lectures, Marks : 25)

Sequential logic design: Latches and Flip flops , S-R Flip flop, J-K Flip flop, T and D type Flip flop, Clocked
and edge triggered Flip flops, master slave flip flop, Registers, Counters (synchronous and asynchronous and
modulo-N), State Table, State Diagrams, counter design using excitation table and equations. , Ring counter
and Johnson counter.
Programmable Logic Devices: Basic concepts- ROM, PLA, PAL, CPLD, FPGA

Unit-4 (18 Lectures, Marks : 25)

Introduction to Verilog: A Brief History of HDL, Structure of HDL Module, Comparison of VHDL and
Verilog, Introduction to Simulation and Synthesis Tools, Test Benches. Verilog Modules, Delays, data flow
style, behavioral style, structural style, mixed design style, simulating design.
Introduction to Language Elements, Keywords, Identifiers, White Space Characters, Comments, format,
Integers, reals and strings. Logic Values, Data Types-net types, undeclared nets, scalars and vector nets,
Register type, Parameters. Expressions, Operands, Operators, types of Expressions
Data flow Modeling and Behavioral Modeling: Data flow Modeling: Continuous assignment, net
declaration assignments, delays, net delays.
Behavioral Modeling: Procedural constructs, timing controls, block statement, procedural assignments,
conditional statement, loop statement, procedural continuous assignment.
Gate level modeling - Introduction, built in Primitive Gates, multiple input gates, Tri-state gates, pull gates,
MOS switches, bidirectional switches, gate delay, array instances, implicit nets, Illustrative Examples (both
combinational and sequential logic circuits).
OR

Introduction to VHDL: A Brief History of HDL, Structure of HDL Module, Comparison of VHDL and
Verilog, Introduction to Simulation and Synthesis Tools, Test Benches. VHDL Modules, Delays, data flow
style, behavioral style, structural style, mixed design style, simulating design.
Introduction to Language Elements, Keywords, Identifiers, White Space Characters, Comments, format.
VHDL terms, describing hardware in VHDL, entity, architectures, concurrent signal assignment, event
scheduling, statement concurrency, structural designs, sequential behavior, process statements, process
declarative region, process statement region, process execution, sequential statements, architecture selection,
configuration statements, power of configurations.
Behavioral Modeling: Introduction to behavioral modeling, inertial delay, transport delay , inertial delay
model, transport delay model, transport vs inertial delay, simulation delta drivers, driver creation, generics,
block statements, guarded blocks.
Sequential Processing: Process statement, sensitivity list, signal assignment vs variable assignment,
sequential statements, IF, CASE ,LOOP, NEXT, ,EXIT and ASSERT statements, assertion BNF, WAIT ON
signal, WAIT UNTIL expression, WAIT FOR time expression, multiple wait conditions, WAIT Time-Out,
Sensitivity List vs WAIT Statement Concurrent Assignment, Passive Processes.
Data types: Object types-signal, variable, constant, Data types –scalar types, composite types, incomplete
types, File Type caveats, subtypes, Subprograms and functions

Suggested Books:

1. M. Morris Mano Digital System Design, Pearson Education Asia,( Fourth Edition )
2. Thomas L. Flyod, Digital Fundamentals, Pearson Education Asia (1994)
3. W. H. Gothmann, Digital Electronics: An Introduction To Theory And Practice, Prentice Hall of
India(2000)
4. R. L. Tokheim, Digital Principles, Schaum’s Outline Series, Tata McGraw- Hill (1994)
5. A Verilog HDL Primer – J. Bhasker, BSP, 2003 II Edition.
6. Verilog HDL-A guide to digital design and synthesis-Samir Palnitkar, Pearson, 2nd edition.

Digital Electronics and Verilog/VHDL Lab (Hardware and Circuit Simulation Software)

1. To verify and design AND, OR, NOT and XOR gates using NAND gates.
2. To convert a Boolean expression into logic gate circuit and assemble it using logic gate IC’s.
3. Design a Half and Full Adder.
4. Design a Half and Full Subtractor.
5. Design a seven segment display driver.
6. Design a 4 X 1 Multiplexer using gates.
7. To build a Flip- Flop Circuits using elementary gates. (RS, Clocked RS, D-type).
8. Design a counter using D/T/JK Flip-Flop.
9. Design a shift register and study Serial and parallel shifting of data.

Experiments in Verlog/VHDL

1. Write code to realize basic and derived logic gates.
2. Half adder, Full Adder using basic and derived gates.
3. Half subtractor and Full Subtractor using basic and derived gates.
4. Clocked D FF, T FF and JK FF (with Reset inputs).
5. Multiplexer (4x1, 8x1) and Demultiplexer using logic gates.
6. Decoder (2x4, 3x8), Encoders and Priority Encoders.
7. Design and simulation of a 4 bit Adder.
8. Code converters (Binary to Gray and vice versa).
9. 2 bit Magnitude comparator.
10. 3 bit Ripple counter.